Recently, undesirable radiation, that is, electromagnetic wave noise generated from electronic equipment, has been a serious problem. As a method to decrease such undesirable radiation, a technique to integrate capacitor elements with large capacity in semiconductor integrated circuit devices and the like has attracted attention. Such capacitor elements have capacitor dielectric layers of dielectric with a high dielectric constant (hereinafter, high dielectric). Moreover, research and development concerning a capacitor element that includes a ferroelectric film having spontaneous polarization characteristics as a dielectric layer has been attracted much attention. Such a capacitor element is needed for practically applying a non-volatile RAM that enables writing and reading with lower operating voltage and higher speed compared to conventional devices.
A conventional semiconductor device having a capacitor element is explained below referring to FIG. 8, a partial cross-sectional view of a conventional semiconductor device.
As shown in FIG. 8, a field oxide film 2 is formed on a silicon substrate 1. The field oxide film 2 surrounds a transistor including a diffused layer 3, a gate insulator (gate oxide) 4 and a gate electrode 5. A first insulating layer 6 covers the transistor and the field oxide film, on which a capacitor element 10, which includes a bottom electrode 7, a capacitor dielectric layer 8 and a top electrode 9, is formed. The capacitor element 10 is covered with a second insulating layer 15 such as a phosphorous doped silicon dioxide film, that is, a PSG film. Some contact holes are formed through the first insulating layer 6 to reach to the diffused layer 3 of the transistor, and others are formed through the second insulating layer 15 to reach to the bottom or top electrode 7, 9 of the capacitor element. Wiring layers 13a, 13b are formed on the insulating layers to have electrical contacts with the element through the contact holes. These elements and layers formed on the silicon substrate 1 are covered with a passivation layer 14.
A conventional method for producing a semiconductor device having a capacitor element is explained below referring to the flow chart of FIG. 9 in addition to FIG. 8.
As shown in FIG. 9, in order to form a transistor (i.e. the "circuit element" shown in FIG. 9), a field oxide layer 2, a diffused layer 3, a gate insulator 4 and a gate electrode 5 are formed in and on a silicon substrate 1. In order to cover the elements and the layers, a first insulating layer 6 is formed, followed by forming a bottom electrode 7, a capacitor dielectric layer 8 and a top electrode 9 on the first insulating layer 6 to make a capacitor element 10. In general, the dielectric layer 8 is heat-treated after forming a pattern of the capacitor element 10 or directly after forming the capacitor dielectric layer 8. For example, the dielectric layer 8 is composed of a high dielectric, while each of the bottom and top electrodes is composed of a platinum film at the closer side to the dielectric and a titanium film at the far side from the dielectric. In order to cover the capacitor element 10, a second insulating layer 15 such as a PSG film is formed by chemical vapor deposition or the like, followed by forming contact holes 12a, 12b to reach the diffused layer 3 or the electrodes 7, 9. Subsequently, wiring layers 13a, 13b are formed on the insulating layers 6, 15 so that some parts of the first wiring layer 13a reach to the diffused layer 3 through the contact holes 12a in the first insulating layer 6, and some parts of the layer 13b reach to the electrodes 7, 9 through the contact holes 12b in the second insulating layer 15. The wiring layers are covered with a passivation layer 14. As a passivation layer 14, a silicon nitride film or a silicon nitride oxide film formed by plasma chemical vapor deposition (plasma CVD) is preferably used because of a high moisture resistance.
In a process for producing a MOS transistor, heat-treatment in a hydrogen atmosphere (hereinafter, hydrogen-treatment) is generally necessary to recover the damaged interface of the silicon substrate with the insulating layer, especially with the gate insulator. However, when a semiconductor device includes a capacitor element with a high dielectric as a capacitor dielectric layer, the high dielectric degrades by hydrogen-treatment.
As a method to solve such degradation of a high dielectric, Japanese Patent Publication No. 7-226443 (Tokkai-Hei No. 7-226443) shows a process, including the steps of: forming a capacitor element above a substrate having an integrated circuit element, forming an interlayer insulator to cover the substrate, forming contact holes through the interlayer insulator to reach the integrated circuit element, and heat-treating the substrate before forming the contact holes to reach the capacitor element. Thus, hydrogen can be supplied to the integrated circuit element that has a damaged interface through the contact holes, while hydrogen cannot easily arrive at the capacitor element because the contact holes have not been formed yet.
Such a process can be applied only before forming the wiring layers. When two or more wiring layers are formed for a multilayer interconnection, it cannot recover the damage generated after forming the first wiring layer at the interface in a MOS transistor. Moreover, as the process cannot effectively prevent hydrogen from arriving at the capacitor element, a capacitor dielectric layer such as a high dielectric containing bismuth that is heavily degraded by hydrogen cannot avoid a change in the characteristics of the capacitor element to some extent.